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Supertex inc.
High Speed 100V 2A Integrated Ultrasound Pulser
Features
HVCMOS technology for high performance 0 to 100V output voltage 2A source and sink current Built-in damping for RTZ waveform capability Gate-clamp for quick output amplitude ramping Up to 40MHz operation frequency 3ns matched delay times Second harmonic is less than -40dB 1.8V to 3.3V CMOS logic interface 7x7 thermally-enhanced 44-lead QFN MCM
HV732
Initial Release
General Description
The Supertex HV732 is a single, complete, high-voltage, high-speed, ultrasound transmitter pulser. It is designed for medical ultrasound imaging applications. The HV732 has built-in damping for faster RTZ waveform capability and high voltage MOSFET gate-clamping function for quick ramping of the output voltage amplitude. The HV732 consists of a control logic circuit, level translators, MOSFET gate drive buffers, clamp circuits, and high current, high voltage MOSFETs as the ultrasound transmitter pulser output stage. In the output stage there are two pairs of MOSFETs. Each pair consists of a P-channel and an N-channel MOSFET. They are designed to have the same impedance, and can provide peak currents of over 2 amps. The built-in MOSFET gate driver outputs swing 0 to 12V on PDR and NDR pins. The P-channel damp output swings 0 to -5V on the DMPO pin.
Application
Medical ultrasound imaging
Typical Application Circuit
PDR
10nF PGATE VPP 0 to +100V TXP
+12V PIN VSUB CLAMP VLL VLN EN VDD GND NIN AVDD AGND +1.8 to 3.3V -5V on/off +5 to 12V 0V +12V Level Trans. Level Trans. Substrate, PAD1 Buffer PAD3 PAD2
Clamp Circuit
TXN
VNN 0 to -100V
HVOUT
OUTN Buffer OUTP
Bias RGNDP
DAMP
Level Trans.
RGNDN NDR NGATE DMPO DMPI
10nF
10nF
NR040506
Supertex inc.
* 1235 Bordeaux Drive, Sunnyvale, CA 94089 * Tel: (408) 222-8888 * FAX: (408) 222-4895 * www.supertex.com
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HV732
Ordering Information
Device
HV732
Power-Up Sequence
1 2 3 4 5 VPP and VSUB VNN VLN VDD VLL 44-Lead QFN
Package Options
HV732K6 HV732K6-G
-G indicates package is RoHS compliant (`Green')
Absolute Maximum Ratings
Parameter VLL, logic supply VDD, positive gate drive supply AVDD, positive gate drive supply VLN, Negative gate drive supply VPP-VNN, differential high voltage supply VPP, high voltage positive supply VNN, high voltage negative supply Storage temperature Thermal enhanced package power dissipation Value -0.5V to +5.5V -0.5V to +15V -0.5V to +15V -5.5V to +0.5V +220V -0.5V to +200V +0.5V to -200V -65C to 150C 1.5W
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Operating Supply Voltages and Current
(Over recommended operating conditions unless otherwise specified: AVDD = VDD = 12V, VLL = 3.3V, VLN = -5V, TA = 25C)
Symbol VLL AVDD VDD VPP VNN VLN VSUB IDDQ IDDEN IDDEN IPPQ IPPEN INNQ
Parameter Logic supply Positive analog supply Positive drive supply High voltage positive supply for HVOUTP1 High voltage negative supply for HVOUTN1 High voltage negative supply for HVOUTN2 High voltage positive supply for to bias substrate VDD current EN = Low VDD current EN = High VDD current at 5MHz PW VDD current EN = Low VDD current EN = High VDD current EN = Low
Min 1.8 9.0 9.0 0 -100 -4.75 -
Typ 3.3 -5.0 175 1.7 7.5 2.0 140 -1.0
Max 3.6 12.6 12.6 100 0 -5.25 100 290 2.8 5.0 180 -3.0
Units V V V V V V V A mA mA A A A
Conditions ------------Need to be the most positive supply on the device --PIN = NIN = Low f = 5.0MHz, PW D% = 1.0% No cap on PDR, NDR VPP = +100V, VNN = -100V PIN = NIN = Low, VPP = +100V, VNN = -100V VPP = +100V, VNN = -100V
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Operating Supply Voltages and Current (cont.)
(Over recommended operating conditions unless otherwise specified: AVDD = VDD = 12V, VLL = 3.3V, VLN = -5V, TA = 25C)
Symbol INNEN ILLQ ILLEN ILNQ ILNEN
Parameter VDD current EN = High VDD current EN = Low VDD current EN = High VDD current EN = Low VDD current EN = High
Min -
Typ -140 1.0 16 -1.0 -230
Max -180 5.0 25 -5.0 -320
Units A A A A A
Conditions PIN = NIN = Low, VPP = +100V, VNN = -100V --PIN = NIN = Low --PIN = NIN = Low
DC Electrical Characteristics
(Over recommended operating conditions unless otherwise specified: AVDD = VDD = 12V, VLL = 3.3V, VLN = -5V, TA = 25C)
Output P-Channel MOSFET, TXP
Symbol IOUT RON RGS VGS VGSF VGS(th) CISS COSS Parameter Output saturation current Channel resistance Gate to source resistor Source to gate zener voltage Gate zener forward voltage Gate threshold voltage Input capacitance Output capacitance Min -2.0 10 -13.2 -0.5 -1.0 Typ 25 Max 8 50 -25 -0.8 -2.4 200 55 Units A K V V V pF pF Conditions VGS = -10V, VDS = -25V VGS = -10V, IDS = -1.0A IGS = -100A IGS = -2.0A --IDS = -1.0mA VGS = 0V, VDS = -25V, f = 1Mhz
Output N-Channel MOSFET, TXN
Symbol IOUT RON RGS VGS VGSF VGS(th) CISS COSS Parameter Output saturation current Channel resistance Gate to source resistor Source to gate zener voltage Gate zener forward voltage Gate threshold voltage Input capacitance Output capacitance 10 13.2 0.5 1.0 Min 2.0 Typ 28 Max 7.0 50 25 0.8 2.0 110 60 Units A K V V V pF pF Conditions VGS = -10V, VDS = -25V VGS = -10V, IDS = -1.0A IGS = -100A IGS = -2.0A --IDS = -1.0mA VGS = 0V, VDS = -25V, f = 1Mhz
Output P-Channel Damp MOSFET, OUTP
Symbol IOUT RON RGS VGS VGSF VGS(th) CISS COSS Parameter Output saturation current Channel resistance Gate to source resistor Source to gate zener voltage Gate zener forward voltage Gate threshold voltage Input capacitance Output capacitance Min -13.2 0.5 -1.0 Typ -1.0 75 Max 30 100 -25 0.8 -2.6 200 60 Units A K V V V pF pF Conditions VGS = -10V, VDS = -25V VGS = -10V, IDS = -1.0A IGS = -100A IGS = -2.0A --IDS = -1.0mA VGS = 0V, VDS = -25V, f = 1Mhz
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HV732
Output N-Channel Damp MOSFET, OUTN
Symbol IOUT RON VGS CISS COSS Parameter Output saturation current Channel resistance Source to gate zener voltage Input capacitance Output capacitance Min 1.0 1.0 Typ Max 22 2.6 110 60 Units A V pF pF Conditions VGS = 10V, VDS = 25V VGS = 10V, IDS = 0.5A IDS = 1.0A VGS = 0V, VDS = 25V, f = 1Mhz
P-Channel Gate Driver Output, PDR
Symbol RSINK RSOURCE IPDR IPDR Parameter Output sink resistance Output source resistance Peak output sink current Peak output source current Min Typ 10 8.0 2.0 -2.0 Max 15 13 Units A A Conditions IPDR = 100mA IPDR = -100mA -----
N-Channel Gate Driver Output, NDR
Symbol RSINK RSOURCE INDR INDR Parameter Output sink resistance Output source resistance Peak output sink current Peak output source current Min Typ 8.0 9.0 1.0 -1.0 Max 13 14 Units A A Conditions INDR = 100mA INDR = -100mA -----
P-Channel Gate Driver Output, DMPO
Symbol RSINK RSOURCE IDMPO IDMPO Parameter Output sink resistance Output source resistance Peak output sink current Peak output source current Min Typ 26 15 0.3 -0.3 Max 30 30 Units A A Conditions IDMPO = 100mA IDMPO = -100mA -----
P-Channel Gate Clamp MOSFET
Symbol IOUT RON COSS Parameter Output saturation current Channel resistance Output capacitance Min Typ 100 60 40 Max 80 Units A pF Conditions ----VGS = 0V, VDS = 25V, f = 1Mhz
N-Channel Gate Clamp MOSFET
Symbol IOUT RON COSS Parameter Output saturation current Channel resistance Output capacitance Min Typ 50 25 40 Max 50 Units A pF Conditions ----VGS = 0V, VDS = 25V, f = 1Mhz
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HV732
Logic Inputs
Symbol tirf VIH VIL IIH IIL Parameter Inputs rise and fall time Input logic high voltage Input logic low voltage Input logic high current Input logic low current Min 0.8VLL 0 -1.0 Typ Max 10 VLL 0.2VLL 1.0 Units ns V V A A Conditions Logic input edge speed requirement ---------
AC Electrical Characteristics
(Over recommended operating conditions unless otherwise specified: AVDD = VDD = 12V, VLL = 3.3V, VLN = -5V, TA = 25C)
Symbol fout tr tf tdr tdf tdelay HD2 tjitter tEN tDMPON(P) tDMPOFF(P) tDMPON(N) tDMPOFF(N) tCLPON(P) tCLPOFF(P) tCLPON(N) tCLPOFF(N) tPWRUP
Parameter Output frequency range Output rise time Output fall time Delay time on rise time Delay time on fall time Delay time matching Second harmonic distortion Output jitter Enable time Damp switch on delay (P) Damp switch off delay (P) Damp switch on delay (N) Damp switch off delay (N) Clamp switch on delay (P) Clamp switch off delay (P) Clamp switch on delay (N) Clamp switch off delay (N) Device power-up delay
Min -
Typ 10 10 12 12 -40 80 30 17 20 13 13 430 490 330 316 150
Max 40 3.0 50 22 26 17 17 1000 1000 550 500 200
Units MHz ns ns ns ns ns dB ps s ns ns ns ns ns ns ns ns s
Conditions See test curcuit and timing diagram
See relevant test circuit and timing diagram. Load = 1.0k/220pF
From device to device 100 resistor load Standard deviation of td samples (1k) See timing diagram OUTP 50 to -15V, 10nF from DMPO to DMPI. See timing diagram. OUTN 50 to +15V. See timing diagram. PGATE 75 to 0V, 10nF to PDR, VPP = +12V. See timing diagram. NGATE 75 to 0V, 10nF to NDR, VNN = -12V. See timing diagram. All power supplies up and stable
Truth Table
Logic Control Inputs EN 1 1 1 1 1 0 PIN 0 1 0 X 0 X NIN 0 0 1 X 0 X CLAMP 0 0 0 1 0 X DAMP 0 0 0 0 1 X Gate Drive Output PDR H L H H H H NDR L L H L L L DMPO H H H H L H HV Output TXP OFF ON OFF OFF OFF OFF TXN OFF OFF ON OFF OFF OFF Damp Output OUTP OFF OFF OFF OFF ON OFF OUTN OFF OFF OFF OFF ON OFF
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HV732
HV732 Test Circuit
10nF PDR PGATE VPP
+12V PIN VSUB CLAMP VLL VLN VDD EN +1.8 to 3.3V -5V on/off +5 to 12V 0V +12V Level Trans. Level Trans. Substrate, PAD1 Buffer
TXP Clamp Circuit PAD3 PAD2 TXN
VNN HVOUT OUTN Buffer OUTP RLOAD
100
GND NIN AVDD Bias AGND DAMP Level Trans.
RGNDP
RGNDN NDR NGATE DMPO DMPI
10nF
10nF
HV732 TX Switching Time Test
+3.3V 10 +12V 10nF +100V 0 to +100V
VLL EN PIN NIN 20MHz 3V0-P CLAMP DAMP VLN
AVDD
VDD
PDR
PGATE
VSUB
VPP TXP TXN OUTN OUTP to Oscilloscope HVOUT RL CL 220pF RGNDP RGNDN 1K
HV732
AGND
GND
NDR
NGATE
DMPO DMPI
VNN
-5V
0 10nF 10nF 0 to -100V
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HV732
HV732 Timing Diagram
30Us EN PIN NIN PDR NDR VPP HVout VNN DAMP CLAMP VPP
2mA 1.5mA 0.175mA
30Us
0V 1us
1us
IAVDD
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HV732
HV732 TX Switching Time Diagram
NIN
50% PIN tdr
50% tr VPP 90% 90% 90%
10% HVOUT
tdf VNN
10% tf
10%
HV732 DAMP Switching Time Diagram
50% DAMP VPP 90% DAMPOUT 10% 0V 10% VNN tDMPOFF(P) tDMPON(N) 50% 50% tDMPON(P) 0V tDMPOFF(N) 90% 50%
HV732 Clamp Switching Time Diagram
50% CLAMP tCLPOFF(P) VPP 50% tCLPON(P) 90% 50% tCLPOFF(N) 90% 50% tCLPON(N) 0V
HVOUT 10% VNN 10%
0V
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HV732
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function DMPO GND NDR VDD VDD VSUB RGNDN OUTN NGATE VNN VNN VNN VNN VNN TXN TXN NC TXP TXP VPP VPP VPP VPP VPP PGATE OUTP RGNDP VSUB VDD VDD PDR GND GND DMPI PIN VLN AVDD AGND VSUB EN DAMP CLAMP VLL NIN Description Output of low voltage drive buffer for P-channel damp, 10nF external cap to pin 34 (DMPI) Drive power ground Output of low voltage drive buffer for N-DMOS, 10nF external cap to pin 9 (NGATE) Positive voltage supply for drive circuitry (+12V) Positive voltage supply for drive circuitry (+12V) Substrate connection of control / driver die chip (connected to the most positive supply, VPP) Ground return of damp N-DMOS source Output of damp N-DMOS drain (open drain output) Gate input of the high voltage N-DMOS, 10nF external cap from pin 3 (NDR) Negative high voltage power supply (-100V) Negative high voltage power supply (-100V) Negative high voltage power supply (-100V) Negative high voltage power supply (-100V) Negative high voltage power supply (-100V) Output of the high voltage N-DMOS drain (open drain output) Output of the high voltage N-DMOS drain (open drain output) No connection Output of the high voltage P-DMOS drain (open drain output) Output of the high voltage P-DMOS drain (open drain output) Positive high voltage power supply (+100V) Positive high voltage power supply (+100V) Positive high voltage power supply (+100V) Positive high voltage power supply (+100V) Positive high voltage power supply (+100V) Gate input of the high voltage P-DMOS, 10nF external cap from pin 31 (PDR) Damp P-DMOS drain (open drain output) Ground return of damp P-DMOS Substrate connection of control / driver die chip (connected to the most positive supply, VPP) Positive voltage supply for drive circuitry (+12V) Positive voltage supply for drive circuitry (+12V) Output of low voltage drive buffer for P-DMOS, 10nF external cap to pin 25 (PGATE) Drive power ground Drive power ground Connects to damp power P-DMOS gate, 10nF cap to pin 1 (DMPO) Input logic control of the high voltage P-DMOS pin 18 &19 (TXP), Hi = on, Low = off Negative low voltage power supply (-5V) Positive analog voltage power supply (+12V) Analog signal ground (0V) Substrate connection of control / driver chip (connected to the most positive supply) Control / drive chip power enable Hi = on, Low = off Input of damp control on both pin 26 (OUTP) and pin 8 (OUTN), Hi = on, Low = off Input of clamp switches on both gates of output P-DMOS and N-DMOS, Hi = on, Low = off Positive voltage supply of low voltage logic (+1.8V to +5V) Input logic control of the high voltage N-DMOS pin 15 & 16 (TXN), Hi = on, Low = off
Note: The three thermal slabs on the bottom of the package must be externally connected PAD1 to VSUB, PAD2 to TXN, and PAD3 to TXP.
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HV732
44-Lead QFN (K6) Package Outline
4.40 [.173] 4.20 [.165] 0.38 [.015] 0.28 [.011] 0.45 [.018] 0.35 [.014] 0.28 [.011] 0.23 [.009] 1
44
3.35 [.141] 3.37 [.133]
7.13 [.281] 6.87 [.271]
PAD1
0.53 [.021] 0.48 [.019]
0.36 [.014] 0.26 [.010] 0.74 [.029] 0.69 [.027] 11 PAD2
(N)
PAD3
(P)
1.77 [.070] 1.57 [.062]TYP
12
0.51 [.020] 0.41 [.016]
1.77 [.070] 1.57 [.062]TYP
22
7.13 [.281] 6.87 [.271]
Top View
1.00 [.039] 0.85 [.033] 0.05 [.002] 0.00 [.000]
Note: 1. Dimensions in mm. [Inch] 2. Radius is 0.127mm 3. Three thermal slabs on the bottom of the package must be externally connected PAD1 to VSUB, PAD2 to TXN, and PAD3 to TXP.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell its products for use in such applications, unless it receives an adequate "product liability indemnification insurance agreement". Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http//www.supertex.com.
(c)2006 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 222-8888 / FAX: (408) 222-4895
Doc.# DSFP - HV732 NR040506
www.supertex.com
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